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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9762* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 12-bit, 125 msps txdac d/a converter functional block diagram 50pf comp1 +1.20v ref avdd acom reflo comp2 current source array 0.1 f +5v segmented switches lsb switches refio fs adj dvdd dcom clock +5v r set 0.1 f clock iouta ioutb 0.1 f latches ad9762 sleep digital data inputs ( db11?b0 ) features member of pin-compatible txdac product family 125 msps update rate 12-bit resolution excellent spurious free dynamic range performance sfdr to nyquist @ 5 mhz output: 70 dbc differential current outputs: 2 ma to 20 ma power dissipation: 175 mw @ 5 v to 45 mw @ 3 v power-down mode: 25 mw @ 5 v on-chip 1.20 v reference single +5 v or +3 v supply operation package: 28-lead soic and tssop edge-triggered latches applications communication transmit channel: basestations (single/multichannel applications) adsl/hfc modems direct digital synthesis (dds) instrumentation product description the ad9762 is the 12-bit resolution member of the txdac series of high performance, low power cmos digital-to-analog converters (dacs). the txdac family which consists of pin compatible 8-, 10-, 12-, and 14-bit dacs is specifically opti- mized for the transmit signal path of communication systems. all of the devices share the same interface options, small outline package and pinout, thus providing an upward or downward component selection path based on performance, resolution and cost. the ad9762 offers exceptional ac and dc performance while supporting update rates up to 125 msps. the ad9762? flexible single-supply operating range of 2.7 v to 5.5 v and low power dissipation are well suited for portable and low power applications. its power dissipation can be further reduced to a mere 45 mw without a significant degradation in performance by lowering the full-scale current output. also, a power-down mode reduces the standby power dissipation to approximately 25 mw. the ad9762 is manufactured on an advanced cmos process. a segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. edge-triggered input latches and a 1.2 v temperature compensated bandgap refer- ence have been integrated to provide a complete monolithic dac solution. flexible supply options support +3 v and +5 v cmos logic families. the ad9762 is a current-output dac with a nominal full-scale output current of 20 ma and > 100 k ? output impedance. txdac is a registered trademark of analog devices, inc. *patent pending. differential current outputs are provided to support single- ended or differential applications. matching between the two current outputs ensures enhanced dynamic performance in a differential output configuration. the current outputs may be tied directly to an output resistor to provide two complemen- tary, single-ended voltage outputs or fed directly into a trans- former. the output voltage compliance range is 1.25 v. the on-chip reference and control amplifier are configured for maximum accuracy and flexibility. the ad9762 can be driven by the on-chip reference or by a variety of external reference voltages. the internal control amplifier which provides a wide (>10:1) adjustment span allows the ad9762 full-scale current to be adjusted over a 2 ma to 20 ma range while maintaining excellent dynamic performance. thus, the ad9762 may oper- ate at reduced power levels or be adjusted over a 20 db range to provide additional gain ranging capabilities. the ad9762 is available in 28-lead soic and tssop pack- ages. it is specified for operation over the industrial tempera- ture range. product highlights 1. the ad9762 is a member of the txdac product family which provides an upward or downward component selection path based on resolution (8 to 14 bits), performance and cost. 2. manufactured on a cmos process, the ad9762 uses a pro- prietary switching technique that enhances dynamic perfor- mance beyond what was previously attainable by higher power/cost bipolar or bicmos devices. 3. on-chip, edge-triggered input cmos latches interface readily to +3 v and +5 v cmos logic families. the ad9762 can support update rates up to 125 msps. 4. a flexible single-supply operating range of 2.7 v to 5.5 v and a wide full-scale current adjustment span of 2 ma to 20 ma allow the ad9762 to operate at reduced power levels. 5. the current output(s) of the ad9762 can be easily config- ured for various single-ended or differential circuit topologies.
dc specifications parameter min typ max units resolution 12 bits dc accuracy 1 integral linearity error (inl) t a = +25 c ?.5 0.75 +2.5 lsb t min to t max ?.0 1.0 +4.0 lsb differential nonlinearity (dnl) t a = +25 c ?.5 0.5 +1.5 lsb t min to t max ?.0 0.75 +2.0 lsb analog output offset error ?.025 +0.025 % of fsr gain error (without internal reference) ?0 2 +10 % of fsr gain error (with internal reference) ?0 1 +10 % of fsr full-scale output current 2 2.0 20.0 ma output compliance range ?.0 +1.25 v output resistance 100 k ? output capacitance 5 pf reference output reference voltage 1.08 1.20 1.32 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance 1 m ? small signal bandwidth (w/o c comp1 ) 4 1.4 mhz temperature coefficients offset drift 0 ppm of fsr/ c gain drift (without internal reference) 50 ppm of fsr/ c gain drift (with internal reference) 100 ppm of fsr/ c reference voltage drift 50 ppm/ c power supply supply voltages avdd 5 2.7 5.0 5.5 v dvdd 2.7 5.0 5.5 v analog supply current (i avdd )2530ma digital supply current (i dvdd ) 6 1.5 2 ma supply current sleep mode (i avdd ) 8.5 ma power dissipation 6 (5 v, i outfs = 20 ma) 133 160 mw power dissipation 7 (5 v, i outfs = 20 ma) 190 mw power dissipation 7 (3 v, i outfs = 2 ma) 45 mw power supply rejection ratio?vdd ?.4 +0.4 % of fsr/v power supply rejection ratio?vdd ?.025 +0.025 % of fsr/v operating range ?0 +85 c notes 1 measured at iouta, driving a virtual ground. 2 nominal full-scale current, i outfs , is 32 the i ref current. 3 use an external buffer amplifier to drive any external load. 4 reference bandwidth is a function of external cap at comp1 pin and signal level. refer to figure 41. 5 for operation below 3 v, it is recommended that the output current be reduced to 12 ma or less to maintain optimum performance. 6 measured at f clock = 25 msps and f out = 1.0 mhz. 7 measured as unbuffered voltage output into 50 ? r load at iouta and ioutb, f clock = 100 msps and f out = 40 mhz. specifications subject to change without notice. (t min to t max , avdd = +5 v, dvdd = +5 v, i outfs = 20 ma, unless otherwise noted) ? rev. b ad9762?pecifications
dynamic specifications parameter min typ max units dynamic performance maximum output update rate (f clock ) 125 msps output settling time (t st ) (to 0.1%) 1 35 ns output propagation delay (t pd )1ns glitch impulse 5 pv-s output rise time (10% to 90%) 1 2.5 ns output fall time (10% to 90%) 1 2.5 ns output noise (i outfs = 20 ma) 50 pa/ hz output noise (i outfs = 2 ma) 30 pa/ hz ac linearity spurious-free dynamic range to nyquist f clock = 25 msps; f out = 1.00 mhz t a = +25 c 75 79 dbc t min to t max 73 dbc f clock = 50 msps; f out = 1.00 mhz 79 dbc f clock = 50 msps; f out = 2.51 mhz 74 dbc f clock = 50 msps; f out = 5.02 mhz 70 dbc f clock = 50 msps; f out = 20.2 mhz 57 dbc f clock = 100 msps; f out = 2.51 mhz 73 dbc f clock = 100 msps; f out = 5.04 mhz 67 dbc f clock = 100 msps; f out = 20.2 mhz 57 dbc f clock = 100 msps; f out = 40.4 mhz 53 dbc spurious-free dynamic range within a window f clock = 25 msps; f out =1.00 mhz; 2 mhz span t a = +25 c 78 86 dbc t min to t max 76 dbc f clock = 50 msps; f out = 5.02 mhz; 2 mhz span 84 dbc f clock = 100 msps; f out = 5.04 mhz; 4 mhz span 84 dbc total harmonic distortion f clock = 25 msps; f out = 1.00 mhz t a = +25 c ?8 ?4 dbc t min to t max ?2 dbc f clock = 50 mhz; f out = 2.00 mhz ?5 dbc f clock = 100 mhz; f out = 2.00 mhz ?5 dbc multitone power ratio (8 tones at 110 khz spacing) f clock = 20 msps; f out = 2.00 mhz to 2.99 mhz 73 dbc notes 1 measured single ended into 50 ? load. specifications subject to change without notice. (t min to t max , avdd = +5 v, dvdd = +5 v, i outfs = 20 ma, differential tran sformer coupled output, 50 doubly terminated, unless otherwise noted) ad9762 ? rev. b
ad9762 ? rev. b digital specifications parameter min typ max units digital inputs logic ??voltage @ dvdd = +5 v 3.5 5 v logic ??voltage @ dvdd = +3 v 2.1 3 v logic ??voltage @ dvdd = +5 v 0 1.3 v logic ??voltage @ dvdd = +3 v 0 0.9 v logic ??current ?0 +10 a logic ??current ?0 +10 a input capacitance 5 pf input setup time (t s ) 2.0 ns input hold time (t h ) 1.5 ns latch pulsewidth (t lpw ) 3.5 ns specifications subject to change without notice. 0.1% 0.1% t s t h t lpw t pd t st db0 db11 clock iouta or ioutb figure 1. timing diagram absolute maximum ratings* with parameter respect to min max units avdd acom ?.3 +6.5 v dvdd dcom ?.3 +6.5 v acom dcom ?.3 +0.3 v avdd dvdd ?.5 +6.5 v clock, sleep dcom ?.3 dvdd + 0.3 v digital inputs dcom ?.3 dvdd + 0.3 v iouta, ioutb acom ?.0 avdd + 0.3 v comp1, comp2 acom ?.3 avdd + 0.3 v refio, fsadj acom ?.3 avdd + 0.3 v reflo acom ?.3 +0.3 v junction temperature +150 c storage temperature ?5 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. ordering guide temperature package package model range description option* ad9762ar ?0 c to +85 c 28-lead 300 mil soic r-28 ad9762aru ?0 c to +85 c 28-lead tssop ru-28 AD9762-EB evaluation board *r = soic, ru = tssop. thermal characteristics thermal resistance 28-lead 300 mil soic ja = 71.4 c/w jc = 23 c/w 28-lead tssop ja = 97.9 c/w jc = 14.0 c/w caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9762 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. (t min to t max , avdd = +5 v, dvdd = +5 v, i outfs = 20 ma unless otherwise noted) warning! esd sensitive device
ad9762 5 rev. b pin configuration 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 ad9762 nc = no connect (msb) db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 nc nc clock dvdd dcom nc avdd comp2 iouta ioutb acom comp1 fs adj refio reflo sleep pin descriptions pin no. name description 1 db11 most significant data bit (msb). 2?1 db10?b1 data bits 1?0. 12 db0 least significant data bit (lsb). 13, 14, 25 nc no internal connection. 15 sleep power-down control input. active high. contains active pull-down circuit, thus may be left u nterminated if not used. 16 reflo reference ground when internal 1.2 v reference used. connect to avdd to disable internal reference. 17 refio reference input/output. serves as reference input when internal reference disabled (i.e., tie reflo to avdd). serves as 1.2 v reference output when internal reference activated (i.e., tie reflo to acom). requires 0.1 f capacitor to acom when internal reference activated. 18 fs adj full-scale current output adjust. 19 comp1 bandwidth/noise reduction node. add 0.1 f to avdd for optimum performance. 20 acom analog common. 21 ioutb complementary dac current output. full-scale current when all data bits are 0s. 22 iouta dac current output. full-scale current when all data bits are 1s. 23 comp2 internal bias node for switch driver circuitry. decouple to acom with 0.1 f capacitor. 24 avdd analog supply voltage (+2.7 v to +5.5 v). 26 dcom digital common. 27 dvdd digital supply voltage (+2.7 v to +5.5 v). 28 clock clock input. data latched on positive edge of clock.
ad9762 6 rev. b definitions of specifications linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (or dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called offset error. for i outa , 0 ma output is expected when the inputs are all 0s. for i outb , 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (+25 c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per degree c. for reference drift, the drift is reported in ppm per degree c. power supply rejection the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. total harmonic distortion thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured output signal. it is expressed as a percentage or in decibels (db). multitone power ratio the spurious-free dynamic range for an output containing mul- tiple carrier tones of equal amplitude. it is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. 50pf comp1 +1.20v ref avdd acom reflo comp2 pmos current source array 0.1 f +5v segmented switches for db11 db3 lsb switches refio fs adj dvdd dcom clock +5v r set 2k 0.1 f dvdd dcom iouta ioutb 0.1 f ad9762 sleep 50 retimed clock output* latches digital data tektronix awg-2021 lecroy 9210 pulse generator clock output 50 20pf 50 20pf 100 to hp3589a spectrum/ network analyzer 50 input mini-circuits t1-1t * awg2021 clock retimed such that digital data transitions on falling edge of 50% duty cycle clock. figure 2. basic ac characterization test set-up
ad9762 7 rev. b typical ac characterization curves @ +5 v supplies (avdd = +5 v, dvdd = +5 v, i outfs = 20 ma, 50 doubly terminated load, differential output, t a = +25 c, sfdr up to nyquist, u nless otherwise noted) frequency mhz sfdr dbc 90 80 50 0.1 100 110 60 70 5msps 25msps 50msps 100msps 125msps figure 3. sfdr vs. f out @ 0 dbfs frequency mhz sfdr dbc 85 50 0.00 5.00 25.00 10.00 15.00 20.00 80 75 70 60 55 65 0dbfs 6dbfs 12dbfs figure 6. sfdr vs. f out @ 50 msps a out dbfs sfdr dbc 85 45 30 25 0 20 15 10 5 75 55 65 455khz @ 5msps 2.27mhz @ 25msps 4.55mhz @ 50msps 9.1mhz @ 100msps 11.37mhz @ 125msps figure 9. single-tone sfdr vs. a out @ f out = f clock /11 frequency mhz sfdr dbc 85 50 0.00 2.50 0.50 1.00 1.50 2.00 80 75 70 60 55 65 0dbfs 6dbfs 12dbfs figure 4. sfdr vs. f out @ 5 msps frequency mhz sfdr dbc 85 50 0.00 10.00 50.00 20.00 30.00 40.00 80 75 70 60 55 65 0dbfs 6dbfs 12dbfs figure 7. sfdr vs. f out @100 msps a out dbfs sfdr dbc 85 45 30 25 0 20 15 10 5 75 55 65 1mhz @ 5msps 5.0mhz @ 25msps 10mhz @ 50msps 20mhz @ 100msps 25mhz @ 125msps figure 10. single-tone sfdr vs. a out @ f out = f clock /5 frequency mhz sfdr dbc 85 50 0.00 2.00 12.00 4.00 6.00 8.00 10.00 80 75 70 60 55 65 0dbfs 6dbfs 12dbfs figure 5. sfdr vs. f out @ 25 msps frequency mhz sfdr dbc 85 50 0.00 10.00 60.00 20.00 30.00 40.00 50.00 80 75 70 60 55 65 0dbfs 6dbfs 12dbfs figure 8. sfdr vs. f out @ 125 msps a out dbfs sfdr dbc 80 40 30 25 0 20 15 10 5 70 50 60 0.675/0.725mhz @ 5msps 3.38/3.63mhz @ 25msps 6.75/7.25mhz @ 50msps 13.5/14.5mhz @ 100msps 16.9/18.1mhz @ 125msps figure 11. dual-tone sfdr vs. a out @ f out = f clock /7
ad9762 8 rev. b frequency msps dbc 70 75 95 0 20 140 40 60 80 100 120 80 85 90 2nd harmonic 3rd harmonic 4th harmonic figure 12. thd vs. f clock @ f out = 2 mhz 1.25 0.50 1.25 4000 error lsb 1000 2000 3000 1.00 0.25 0.25 0 0.75 0.50 1.00 0.75 code 0 figure 15. typical inl 10db div 0 100 start: 0.3 mhz stop: 50.0 mhz f clock = 100 msps f out = 2.41mhz sfdr = 72dbc amplitude = 0dbfs figure 18. single-tone sfdr i outfs ma sfdr dbc 80 70 30 28 20 14 60 50 40 75 65 55 45 35 4 6 10 12 16 18 2.5mhz 10mhz 22.2mhz 40mhz figure 13. sfdr vs. f out and i outfs @ 100 msps, 0 dbfs 1 0.4 4000 error lsb 1000 2000 3000 0.8 0.2 0.2 0 0.4 0.6 code 0 figure 16. typical dnl 10db div 0 100 start: 0.3 mhz stop: 50.0 mhz f clock = 100 msps f out1 = 13.5mhz f out2 = 14.5mhz sfdr = 62dbc amplitude = 0dbfs figure 19. dual-tone sfdr output frequency mhz sfdr dbc 75 70 45 1 10 100 60 55 50 65 idiff @ 6dbfs idiff @ 0dbfs iouta @ 6dbfs iouta @ 0dbfs figure 14. differential vs. single- ended sfdr vs. f out @ 100 msps temperature c sfdr dbc 80 75 50 40 20 80 60 70 65 60 55 40 20 0 2.5mhz 10mhz 40mhz figure 17. sfdr vs. temperature @ 100 msps, 0 dbfs 10db div 10 110 start: 0.3 mhz stop: 25.0 mhz f clock = 50 msps f out1 = 6.25mhz f out2 = 6.75mhz f out3 = 7.25mhz f out4 = 7.75mhz sfdr = 71dbc amplitude = 0dbfs figure 20. four-tone sfdr
ad9762 9 rev. b frequency mhz sfdr dbc 90 80 50 0.1 100 110 60 70 5msps 25msps 50msps 100msps 125msps figure 21. sfdr vs. f out @ 0 dbfs frequency mhz sfdr dbc 85 50 05 25 10 15 20 80 75 70 60 55 65 0dbfs 6dbfs 12dbfs figure 24. sfdr vs. f out @ 50 msps a out dbfs sfdr dbc 90 50 30 25 0 20 15 10 5 80 60 70 455khz @ 5msps 2.27mhz @ 25msps 4.55mhz @ 50msps 9.1mhz @ 100msps 11.37mhz @ 125msps 40 figure 27. single-tone sfdr vs. a out @ f out = f clock /11 typical ac characterization curves @ +3 v supplies (avdd = +3 v, dvdd = +3 v, i outfs = 20 ma, 50 ? doubly terminated load, differential output, t a = +25 c, sfdr up to nyquist, unless otherwise noted) frequency mhz sfdr dbc 85 50 0.00 2.50 0.50 1.00 1.50 2.00 80 75 70 60 55 65 0dbfs 6dbfs 12dbfs figure 22. sfdr vs. f out @ 5 msps frequency mhz sfdr dbc 85 50 010 50 20 30 40 80 75 70 60 55 65 0dbfs 6dbfs 12dbfs figure 25. sfdr vs. f out @ 100 msps a out dbfs sfdr dbc 90 50 30 25 0 20 15 10 5 80 60 70 1mhz @ 5msps 5.0mhz @ 25msps 10mhz @ 50msps 20mhz @ 100msps 25mhz @ 125msps 40 figure 28. single-tone sfdr vs. a out @ f out = f clock /5 frequency mhz sfdr dbc 85 50 02 12 46 8 10 80 75 70 60 55 65 0dbfs 6dbfs 12dbfs figure 23. sfdr vs. f out @ 25 msps frequency mhz sfdr dbc 85 50 010 60 20 30 40 50 80 75 70 60 55 65 0dbfs 6dbfs 12dbfs figure 26. sfdr vs. f out @ 125 msps a out dbfs sfdr dbc 80 40 30 25 0 20 15 10 5 70 50 60 0.675/0.725mhz @ 5msps 3.38/3.63mhz @ 25msps 6.75/7.25mhz @ 50msps 13.5/14.5mhz @ 100msps 16.9/18.1mhz @ 125msps 90 figure 29. dual-tone sfdr vs. a out @ f out = f clock /7
ad9762 10 rev. b frequency msps dbc 70 75 95 0 20 140 40 60 80 100 120 80 85 90 2nd harmonic 3rd harmonic 4th harmonic figure 30. thd vs. f clock @ f out = 2 mhz 1.25 0.50 1.25 4000 error lsb 1000 2000 3000 1.00 0.25 0.25 0 0.75 0.50 1.00 0.75 code 0 figure 33. typical inl 10db div 0 100 start: 0.3 mhz stop: 50.0 mhz f clock = 100 msps f out = 2.41mhz sfdr = 72dbc amplitude = 0dbfs figure 36. single-tone sfdr i outfs ma sfdr dbc 80 70 30 24 20 14 60 50 40 75 65 55 45 35 6 8 10 12 16 18 2.5mhz 10mhz 22.2mhz 40mhz figure 31. sfdr vs. f out and i outfs @ 100 msps, 0 dbfs 1 0.4 4000 error lsb 1000 2000 3000 0.8 0.2 0.2 0 0.4 0.6 code 0 figure 34. typical dnl 10db div 0 100 start: 0.3 mhz stop: 50.0 mhz f clock = 100 msps f out1 = 13.5mhz f out2 = 14.5mhz sfdr = 59.0dbc amplitude = 0dbfs figure 37. dual-tone sfdr output frequency mhz sfdr dbc 75 70 45 1 10 100 60 55 50 65 idiff @ 6dbfs idiff @ 0dbfs iouta @ 6dbfs iouta @ 0dbfs figure 32. differential vs. single ended sfdr vs. f out @ 100 msps temperature c sfdr dbc 80 75 50 40 20 80 60 70 65 60 55 40 20 0 2.5mhz 10mhz 28.6mhz figure 35. sfdr vs. temperature @ 100 msps, 0 dbfs 10db div 10 110 start: 0.3 mhz stop: 25.0 mhz f clock = 50 msps f out1 = 6.25mhz f out2 = 6.75mhz f out3 = 7.25mhz f out4 = 7.75mhz sfdr = 71dbc amplitude = 0dbfs figure 38. four-tone sfdr
ad9762 11 rev. b functional description figure 39 shows a simplified block diagram of the ad9762. the ad9762 consists of a large pmos current source array that is capable of providing up to 20 ma of total current. the array is divided into 31 equal currents that make up the 5 most significant bits (msbs). the next 4 bits or middle bits consist of 15 equal current sources whose value is 1/16th of an msb current source. the remaining lsbs are binary weighted frac tions of the middle-bits current sources. implementing the m iddle and lower bits with current sources, instead of an r-2r ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the dac? high output impedance (i.e., >100 k ? ). all of these current sources are switched to one or the other of the two output nodes (i.e., i outa or i outb ) via pmos differen- tial current switches. the switches are based on a new archi- tecture that drastically improves distortion performance. this new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. the analog and digital sections of the ad9762 have separate power supply inputs (i.e., avdd and dvdd) that can operate independently over a 2.7 volt to 5.5 volt range. the digital section, which is capable of operating up to a 125 msps clock rate, consists of edge-triggered latches and segment decoding logic circuitry. the analog section includes the pmos current sources, the associated differential switches, a 1.20 v bandgap voltage reference and a reference control amplifier. the full-scale output current is regulated by the reference control amplifier and can be set from 2 ma to 20 ma via an external resistor, r set . the external resistor, in combination with both the reference control amplifier and voltage refer- ence v refio , sets the reference current i ref , which is mirrored over to the segmented current sources with the proper scaling factor. the full-scale current, i outfs , is thirty-two times the value of i ref . dac transfer function the ad9762 provides complementary current outputs, i outa and i outb . i outa will provide a near full-scale current output, i outfs , when all bits are high (i.e., dac code = 4095) while i outb , the complementary output, provides no current. the current output appearing at i outa and i outb is a function of both the input code and i outfs and can be expressed as: i outa = ( dac code /4096) i outfs (1) i outb = (4095 ? dac code )/4096 i outfs (2) where dac code = 0 to 4095 (i.e., decimal representation). as mentioned previously, i outfs is a function of the reference current i ref , which is nominally set by a reference voltage v refio and external resistor r set . it can be expressed as: i outfs = 32 i ref (3) where i ref = v refio / r set (4) the two current outputs will typically drive a resistive load directly or via a transformer. if dc coupling is required, i outa and i outb should be directly connected to matching resistive loads, r load , which are tied to analog common, acom. note, r load may represent the equivalent load resistance seen by i outa or i outb as would be the case in a doubly terminated 50 ? or 75 ? cable. the single-ended voltage output appearing at the i outa and i outb nodes is simply : v outa = i outa r load (5) v outb = i outb r load (6) note the full-scale value of v outa and v outb should not exceed the specified output compliance range to maintain specified distortion and linearity performance. the differential voltage, v diff , appearing across i outa and i outb is: v diff = ( i outa ?i outb ) r load (7) substituting the values of i outa , i outb , and i ref ; v diff can be expressed as: v diff = {(2 dac code ?4095)/4096} (32 r load / r set ) v refio (8) these last two equations highlight some of the advantages of operating the ad9762 differentially. first, the differential operation will help cancel common-mode error sources associ ated with i outa and i outb such as noise, distortion and dc offsets. second, the differential code dependent current and subsequent voltage, v diff , is twice the value of the single-ended voltage output (i.e., v outa or v outb ), thus providing twice the signal power to the load. note, the gain drift temperature performance for a single-ended (v outa and v outb ) or differential output (v diff ) of the ad9762 can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relationship as shown in equation 8. digital data inputs ( db11 db0 ) 50pf comp1 +1.20v ref avdd acom reflo comp2 pmos current source array 0.1 f +5v segmented switches for db11 db3 lsb switches refio fs adj dvdd dcom clock +5v r set 2k 0.1 f iouta ioutb 0.1 f ad9762 sleep latches i ref v refio clock i outb i outa r load 50 v outb v outa r load 50 v diff = v outa v outb figure 39. functional block diagram
ad9762 12 rev. b reference operation the ad9762 contains an internal 1.20 v bandgap reference that can be easily disabled and overridden by an external refer- ence. refio serves as either an input or output depending on whether the internal or an external reference is selected. if reflo is tied to acom, as shown in figure 40, the internal reference is activated and refio provides a 1.20 v output. in this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 f or greater from refio to reflo. also, refio should be buffered with an external amplifier having an input bias current less than 100 na if any additional loading is required. 50pf comp1 +1.2v ref avdd reflo current source array 0.1 f +5v refio fs adj 2k 0.1 f ad9762 additional load optional external ref buffer figure 40. internal reference configuration the internal reference can be disabled by connecting reflo to avdd. in this case, an external reference may then be applied to refio as shown in figure 41. the external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. note that the 0.1 f compensation capacitor is not required since the internal reference is disabled, and the high input impedance (i.e., 1 m ? ) of refio minimizes any loading of the external reference. 50pf comp1 +1.2v ref avdd reflo current source array 0.1 f avdd refio fs adj r set ad9762 external ref i ref = v refio /r set avdd reference control amplifier v refio figure 41. external reference configuration reference control amplifier the ad9762 also contains an internal control amplifier that is used to regulate the dac? full-scale output current, i outfs . the control amplifier is configured as a v-i converter as shown in figure 41, such that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 4. i ref is copied over to the segmented current sources with the proper scaling factor to set i outfs as stated in equation 3. the control amplifier allows a wide (10:1) adjustment span of i outfs over a 2 ma to 20 ma range by setting iref between 62.5 a and 625 a. the wide adjustment span of i outfs provides several application benefits. the first benefit relates directly to the power dissipation of the ad9762, which is proportional to i outfs (refer to the power dissipation section). the second benefit relates to the 20 db adjustment, which is useful for system gain control purposes. the small signal bandwidth of the reference control amplifier is approximately 1.4 mhz and can be reduced by connecting an external capacitor between comp1 and avdd. the output of the control amplifier, comp1, is internally compensated via a 50 pf capacitor that limits the control amplifier small-signal bandwidth and reduces its output impedance. any additional external capacitance further limits the bandwidth and acts as a filter to reduce the noise contribution from the reference ampli- fier. figure 42 shows the relationship between the external capacitor and the small signal ? db bandwidth of the comp1 capacitor nf 1000 0.1 1000 bandwidth khz 10 1 10 100 0 figure 42. external comp1 capacitor vs. 3 db bandwidth reference amplifier. since the ? db bandwidth corresponds to the dominant pole, and hence the time constant, the settling time of the control amplifier to a stepped reference input response can be approximated. the optimum distortion performance for any reconstructed waveform is obtained with a 0.1 f external capacitor installed. thus, if i ref is fixed for an application, a 0.1 f ceramic chip capacitor is recommended. also, since the control amplifier is optimized for low power operation, multiplying applications requiring large signal swings should consider using an external control amplifier to enhance the application? overall large signal multiplying bandwidth and/or distortion performance. there are two methods in which i ref can be varied for a fixed r set . the first method is suitable for a single-supply system in which the internal reference is disabled, and the common-mode voltage of refio is varied over its compliance range of 1.25 v to 0.10 v. refio can be driven by a single-supply amplifier or dac, thus allowing i ref to be varied for a fixed r set . since the input impedance of refio is approximately 1 m ? , a simple, low cost r-2r ladder dac configured in the voltage mode topology may be used to control the gain. this circuit is shown in figure 43 using the ad7524 and an external 1.2 v reference, the ad1580.
ad9762 13 rev. b the second method may be used in a dual-supply system in which the common-mode voltage of refio is fixed and i ref is varied by an external voltage, v gc , applied to r set via an ampli- fier. an example of this method is shown in figure 44 in which the internal reference is used to set the common-mode voltage of the control amplifier to 1.20 v. the external voltage, v gc , is referenced to acom and should not exceed 1.2 v. the value of r set is such that i refmax and i refmin do not exceed 62.5 a and 625 a, respectively. the associated equations in figure 44 can be used to determine the value of r set . 50pf comp1 +1.2v ref avdd reflo current source array avdd refio fs adj r set ad9762 i ref optional bandlimiting capacitor v gc 1 f i ref = (1.2 v gc )/r set with v gc < v refio and 62.5 a i ref 625a figure 44. dual-supply gain control circuit in some applications, the user may elect to use an external con- trol amplifier to enhance the multiplying bandwidth, distortion performance, and/or settling time. external amplifiers capable of driving a 50 pf load such as the ad817 are suitable for this purpose. it is configured in such a way that it is in parallel with the weaker internal reference amplifier as shown in figure 45. in this case, the external amplifier simply overdrives the weaker reference control amplifier. also, since the internal control amplifier has a limited current output, it will sustain no damage if overdriven. 50pf comp1 +1.2v ref avdd reflo current source array avdd refio fs adj r set ad9762 v ref input external control amplifier figure 45. configuring an external reference control amplifier analog outputs the ad9762 produces two complementary current outputs, i outa and i outb , which may be configured for single-ended or differential operation. i outa and i outb can be converted into complementary single-ended voltage outputs, v outa and v outb , via a load resistor, r load , as described in the dac transfer function section by equations 5 through 8. the differential voltage, v diff , existing between v outa and v outb can also be converted to a single-ended voltage via a transformer or differ- ential amplifier configuration. the ac performance of the ad9762 is optimum and specified using a differential trans- former coupled output in which the voltage swing at i outa and i outb is limited to 0.5 v. if a single-ended unipolar output is desirable, i outa should be selected. the distortion and noise performance of the ad9762 can be enhanced when the ad9762 is configured for differential opera- tion. the common-mode error sources of both i outa and i outb can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. these common-mode error sources include even-order distortion products and noise. the enhancement in distortion performance becomes more significant as the frequency content of the reconstructed wave- form increases. this is due to the first order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough and noise. performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the recon- structed signal power to the load (i.e., assuming no source termination). since the output currents of i outa and i outb are complementary, they become additive when processed differen- tially. a properly selected transformer will allow the ad9762 to provide the required power and voltage levels to different loads. refer to applying the ad9762 section for examples of various output configurations. the output impedance of i outa and i outb is determined by the equivalent parallel combination of the pmos switches associ- ated with the current sources and is typically 100 k ? in parallel with 5 pf. it is also slightly dependent on the output voltage (i.e., v outa and v outb ) due to the nature of a pmos device. as a result, maintaining i outa and/or i outb at a virtual ground via an i-v op amp configuration will result in the optimum dc linearity. note, the inl/dnl specifications for the ad9762 are measured with i outa maintained at a virtual ground via an op amp. 1.2v 50pf comp1 +1.2v ref avdd reflo current source array avdd refio fs adj r set ad9762 i ref = v ref /r set avdd optional bandlimiting capacitor v ref v dd r fb out1 out2 agnd db7 db0 ad7524 ad1580 0.1v to 1.2v figure 43. single-supply gain control circuit
ad9762 14 rev. b i outa and i outb also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. the negative output compliance range of ?.0 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a break- down of the output stage and affect the reliability of the ad9762. the positive output compliance range is slightly dependent on the full-scale output current, i outfs . it degrades slightly from its nominal 1.25 v for an i outfs = 20 ma to 1.00 v for an i outfs = 2 ma. the optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at i outa and i outb does not exceed 0.5 v. applications requiring the ad9762? output (i.e., v outa and/ or v outb ) to extend its output compliance range should size r load accordingly. operation beyond this compliance range will adversely affect the ad9762? linearity performance and subsequently degrade its distortion performance. digital inputs the ad9762? digital input consists of 12 data input pins and a clock input pin. the 12-bit parallel data inputs follow standard positive binary coding where db11 is the most significant bit (msb) and db0 is the least significant bit (lsb). i outa produces a full-scale output current when all data bits are at logic 1. i outb produces a complementary output with the full-scale current split between the two outputs as a function of the input code. the digital interface is implemented using an edge-triggered master slave latch. the dac output is updated following the rising edge of the clock as shown in figure 1 and is designed to support a clock rate as high as 125 msps. the clock can be operated at any duty cycle that meets the specified latch pulsewidth. the set-up and hold times can also be varied within the clock cycle as long as the specified minimum times are met; although the location of these transition edges may affect digital feedthrough and distortion performance. best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock . the digital inputs are cmos compatible with logic thresholds, v threshold set to approximately half the digital positive supply (dvdd) or v threshold = dvdd /2 ( 20%) the internal digital circuitry of the ad9762 is capable of oper ating over a digital supply range of 2.7 v to 5.5 v. as a result, the digital inputs can also accommodate ttl levels when dvdd is set to accommodate the maximum high level voltage of the ttl drivers v oh(max) . a dvdd of 3 v to 3.3 v will typically ensure proper compatibility with most ttl logic families. figure 46 shows the equivalent digital input circuit for the data and clock inputs. the sleep mode input is similar with the exception that it contains an active pull-down circuit, thus ensuring that the ad9762 remains enabled if this input is left disconnected. dvdd digital input figure 46. equivalent digital input since the ad9762 is capable of being updated up to 125 msps, the quality of the clock and data input signals are important in achieving the optimum performance. the drivers of the digital data interface circuitry should be specified to meet the minimum set-up and hold times of the ad9762 as well as its required min/max input logic level thresholds. typically, the selection of the slowest logic family that satisfies the above conditions will result in the lowest data feedthrough and noise. digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. the insertion of a low value resistor network (i.e., 20 ? to 100 ? ) between the ad9762 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to data feedthrough. for longer run lengths and high data update rates, strip line techniques with proper termination resistors should be considered to maintain ?lean?digital inputs. also, operating the ad9762 with reduced logic swings and a corresponding digital supply (dvdd) will also reduce data feedthrough. the external clock driver circuitry should provide the ad9762 with a low jitter clock input meeting the min/max logic levels while providing fast edges. fast clock edges will help minimize any jitter that will manifest itself as phase noise on a recon- structed waveform. thus, the clock input should be driven by the fastest logic family suitable for the application. note, the clock input could also be driven via a sine wave, which is centered around the digital threshold (i.e., dvdd/2), and meets the min/max logic threshold. this will typically result in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. also, at higher sampling rates, the 20% tolerance of the digital logic threshold should be considered since it will affect the effective clock duty cycle and subsequently cut into the required data set-up and hold times. sleep mode operation the ad9762 has a power-down function which turns off the output current and reduces the supply current to less than 8.5 ma over the specified supply range of 2.7 v to 5.5 v and temperature range. this mode can be activated by applying a logic level ??to the sleep pin. this digital input also contains an active pull-down circuit that ensures the ad9762 remains enabled if this input is left disconnected. the sleep input with active pull-down requires <40 a of drive current. the power-up and power-down characteristics of the ad9762 are dependent upon the value of the compensation capacitor connected to comp1. with a nominal value of 0.1 f, the ad9762 takes less than 5 s to power down and approximately 3.25 ms to power back up. note, the sleep mode should not be used when the external control amplifier is used as shown in figure 45. power dissipation the power dissipation, p d , of the ad9762 is dependent on several factors which include: (1) avdd and dvdd, the power supply voltages; (2) i outfs , the full-scale current output; (3) f clock , the update rate; (4) and the reconstructed digital input waveform. the power dissipation is directly proportional to the analog supply current, i avdd , and the digital supply current, i dvdd . i avdd is directly proportional to i outfs as shown in figure 47 and is insensitive to f clock .
ad9762 15 rev. b i outfs ma 30 0 220 4 6 8 10 12141618 25 20 15 10 5 i avdd ma figure 47. i avdd vs. i outfs conversely, i dvdd is dependent on both the digital input wave- form, f clock , and digital supply dvdd. figures 48 and 49 show i dvdd as a function of full-scale sine wave output ratios (f out /f clock ) for various update rates with dvdd = 5 v and dvdd = 3 v, respectively. note, how i dvdd is reduced by more than a factor of 2 when dvdd is reduced from 5 v to 3 v. ratio (f out /f clk ) 18 16 0 0.01 1 0.1 i dvdd ma 8 6 4 2 12 10 14 5msps 25msps 50msps 100msps 125msps figure 48. i dvdd vs. ratio @ dvdd = 5 v ratio (f out /f clk ) 8 0 0.01 1 0.1 i dvdd ma 6 4 2 5msps 25msps 50msps 100msps 125msps figure 49. i dvdd vs. ratio @ dvdd = 3 v applying the ad9762 output configurations the following sections illustrate some typical output configura- tions for the ad9762. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma. for applications requir- ing the optimum dynamic performance, a differential output configuration is suggested. a differential output configuration may consist of either an rf transformer or a differential op amp configuration. the transformer configuration provides the optimum high frequency performance and is recommended for any application allowing for ac coupling. the differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain and/or level shifting. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage will result if i outa and/or i outb is connected to an appropriately sized load resistor, r load , referred to acom. this configura- tion may be more suitable for a single-supply system requiring a dc coupled, ground referred output voltage. alternatively, an amplifier could be configured as an i-v converter thus converting i outa or i outb into a negative unipolar voltage. this configura- tion provides the best dc linearity since i outa or i outb is maintained at a virtual ground. note, i outa provides slightly better performance than i outb . differential coupling using a transformer an rf transformer can be used to perform a differential-to- single-ended signal conversion as shown in figure 50. a differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer? passband. an rf transformer such as the mini-circuits t1-1t provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. trans- formers with different impedance ratios may also be used for impedance matching purposes. note that the transformer provides ac coupling only. r load ad9762 22 21 mini-circuits t1-1t optional r diff iouta ioutb figure 50. differential output using a transformer the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc current path for both i outa and i outb . the complementary voltages appear- ing at i outa and i outb (i.e., v outa and v outb ) swing symmetri- cally around acom and should be maintained with the specified output compliance range of the ad9762. a differential resistor, r diff , may be inserted in applications in which the output of the transformer is connected to the load, r load , via a passive reconstruction filter or cable. r diff is determined by the transformer? impedance ratio and provides the proper source termination which results in a low vswr. note that approxi- mately half the signal power will be dissipated across r diff .
ad9762 16 rev. b differential using an op amp an op amp can also be used to perform a differential to single- ended conversion as shown in figure 51. the ad9762 is configured with two equal load resistors, r load , of 25 ? . the differential voltage developed across i outa and i outb is converted to a single-ended signal via the differential op amp configuration. an optional capacitor can be installed across i outa and i outb forming a real pole in a low-pass filter. the addition of this capacitor also enhances the op amps distortion performance by preventing the dacs high slewing output from overloading the op amp? input. ad9762 22 iouta ioutb 21 c opt 500 225 225 500 25 25 ad8047 figure 51. dc differential coupling using an op amp the common-mode rejection of this configuration is typically determined by the resistor matching. in this circuit, the differ- ential op amp circuit using the ad8047 is configured to provide some additional signal gain. the op amp must operate off of a dual supply since its output is approximately 1.0 v. a high speed amplifier capable of preserving the differential perfor- mance of the ad9762 while meeting other system level objec- tives (i.e., cost, power) should be selected. the op amps differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when opti- mizing this circuit. the differential circuit shown in figure 52 provides the neces- sary level-shifting required in a single supply system. in this case, avdd which is the positive analog supply for both the ad9762 and the op amp is also used to level-shift the differ- ential output of the ad9762 to midsupply (i.e., avdd/2). the ad8041 is a suitable op amp for this application. ad9762 22 iouta ioutb 21 c opt 500 225 225 1k 25 25 ad8041 1k avdd figure 52. single-supply dc differential coupled circuit single-ended unbuffered voltage output figure 53 shows the ad9762 configured to provide a unipolar output range of approximately 0 v to +0.5 v for a doubly termi- nated 50 ? cable since the nominal full-scale current, i outfs , of 20 ma flows through the equivalent r load of 25 ? . in this case, r load represents the equivalent load resistance seen by i outa or i outb . the unused output (i outa or i outb ) can be connected to acom directly or via a matching r load . different values of i outfs and r load can be selected as long as the posi tive compliance range is adhered to. one additional consideration in this mode is the integral nonlinearity (inl) as discussed in the analog output section of this data sheet. for optimum inl performance, the single-ended, buffered voltage output configu- ration is suggested. ad9762 iouta ioutb 21 50 25 50 v outa = 0 to +0.5v i outfs = 20ma 22 figure 53. 0 v to +0.5 v unbuffered voltage output single-ended, buffered voltage output configuration figure 54 shows a buffered single-ended output configuration in which the op amp u1 performs an i-v conversion on the ad9762 output current. u1 maintains i outa (or i outb ) at a virtual ground, thus minimizing the nonlinear output imped- ance effect on the dac? inl performance as discussed in the analog output section. although this single-ended configu- ration typically provides the best dc linearity performance, its ac distortion performance at higher dac update rates may be limited by u1? slewing capabilities. u1 provides a negative unipolar output voltage and its full-scale output voltage is sim- ply the product of r fb and i outfs . the full-scale output should be set within u1? voltage output swing capabilities by scaling i outfs and/or r fb . an improvement in ac distortion perfor- mance may result with a reduced i outfs since the signal current u1 will be required to sink will be subsequently reduced. iouta ioutb c opt 200 u1 v out = i outfs r fb i outfs = 10ma r fb 200 ad9762 21 22 figure 54. unipolar buffered voltage output power and grounding considerations in systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. proper rf techniques must be used in device selection; placement and routing; and supply bypassing and grounding. figures 60?5 illustrate the recommended printed circuit board ground, power and signal plane layouts which are implemented on the ad9762 evaluation board. proper grounding and decoupling should be a primary objective in any high speed, high resolution system. the ad9762 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. in general, avdd, the analog supply, should be decoupled to acom, the analog common, as close to the chip as physi- cally possible. similarly, dvdd, the digital supply, should be decoupled to dcom as close as physically as possible.
ad9762 17 rev. b for those applications that require a single +5 v or +3 v supply for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in figure 55. the circuit consists of a differential lc filter with separate power supply and return lines. lower noise can be attained using low esr type electrolytic and tantalum capacitors. 100 f elect. 10-22 f tant. 0.1 f cer. ttl/cmos logic circuits +5v or +3v power supply ferrite beads avdd acom figure 55. differential lc filter for single +5 v or +3 v applications maintaining low noise on power supplies and ground is critical to obtaining optimum results from the ad9762. if properly implemented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding, current trans- port, etc. in mixed signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces, and the digital ground plane confined to areas covering the digital interconnects. all analog ground pins of the dac, reference and other analog components should be tied directly to the analog ground plane. the two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the dac to maintain optimum performance. care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. on the digital side, this includes the digital input lines running to the dac as well as any clock signals. on the analog side, this includes the dac output signal, reference signal and the supply feeders. the use of wide runs or planes in the routing of power lines is also recommended. this serves the dual role of providing a low series impedance power supply to the part, as well as providing some ?ree?capacitive decoupling to the appropriate ground plane. it is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. it is recommended that all connections be short, direct and as physically close to the package as possible in order to minimize the sharing of conduc- tion paths between different currents. when runs exceed an inch in length, strip line techniques with proper termination resistor should be considered. the necessity and value of this resistor will be dependent upon the logic family used. for a more detailed discussion of the implementation and construction of high speed, mixed signal printed circuit boards, refer to analog devices?application notes an-280 and an-333. applications using the ad9762 for qam modulation qam is one of the most widely used digital modulation schemes in digital communication systems. this modulation technique can be found in both fdm as well as spreadspectrum (i.e., cdma) based systems. a qam signal is a carrier frequency which is both modulated in amplitude (i.e., am modulation) and in phase (i.e., pm modulation). it can be generated by independently modulating two carriers of identical frequency but with a 90 phase difference. this results in an in-phase (i) carrier component and a quadrature (q) carrier component at a 90 phase shift with respect to the i component. the i and q components are then summed to provide a qam signal at the specified carrier frequency. a common and traditional implementation of a qam modu- lator is shown in figure 56. the modulation is performed in the analog domain in which two dacs are used to generate the baseband i and q components, respectively. each component is then typically applied to a nyquist filter before being applied to a quadrature mixer. the matching nyquist filters shape and limit each component? spectral envelope while minimizing intersymbol interference. the dac is typically updated at the qam symbol rate or possibly a multiple of it if an interpolating filter precedes the dac. the use of an interpolating filter typi- cally eases the implementation and complexity of the analog filter, which can be a significant contributor to mismatches in gain and phase between the two baseband channels. a quadra- ture mixer modulates the i and q components with in-phase and quadrature phase carrier frequency and then sums the two outputs to provide the qam signal. ad9762 0 90 ad9762 carrier frequency 12 12 to mixer dsp or asic nyquist filters quadrature modulator figure 56. typical analog qam architecture in this implementation, it is much more difficult to maintain proper gain and phase matching between the i and q channels. the circuit implementation shown in figure 57 helps improve upon the matching and temperature stability characteristics between the i and q channels. using a single voltage reference derived from u1 to set the gain for both the i and q channels will improve the gain matching and stability. further enhance- ments in gain matching and stability are achieved by using separate matching resistor networks for both r set and r load . additional trim capability via r cal1 and r cal2 can be added to compensate for any initial mismatch in gain between the two channels. this may be attributed to any mismatch between u1 and u2? gain setting resistor, (r set ); effective load resistance, (r load ); and/or voltage offset of each dac? control amplifier. the differential voltage outputs of u1 and u2 are fed into their respective differential inputs of a quadrature mixer via matching 50 ? filter networks.
ad9762 18 rev. b refio fs adj iouta ioutb clock r set 2k * r cal1 50 clock u1 i-channel 50 ** r load 50 ** r load to nyquist filter and mixer refio fs adj iouta ioutb clock r set 2k * r cal2 100 u2 q-channel 50 ** r load 50 ** r load to nyquist filter and mixer 0.1 f reflo reflo avdd * ohmtek orna1001f ** ohmtek tomc1603-50f figure 57. baseband qam implementation using two ad9762s it is also possible to generate a qam signal completely in the digital domain via a dsp or asic, in which case only a single dac of sufficient resolution and performance is required to reconstruct the qam signal. also available from several vendors are digital asics which implement other digital modulation schemes such as psk and fsk. this digital implementation has the benefit of generating perfectly matched i and q components in terms of gain and phase, which is essential in maintaining optimum performance in a communication system. in this implementation, the reconstruction dac must be operating at a sufficiently high clock rate to accommodate the highest specified qam carrier frequency. figure 58 shows a block diagram of such an implementation using the ad9762. 50 ad9762 lpf 50 to mixer stel-1130 qam 12 cos 12 sin 12 12 i data q data 12 carrier frequency 12 stel-1177 nco clock figure 58. digital qam architecture ad9762 evaluation board general description the AD9762-EB is an evaluation board for the ad9762 12-bit d/a converter. careful attention to layout and circuit design combined with a prototyping area allow the user to easily and effectively evaluate the ad9762 in any application where high resolution, high speed conversion is required. this board allows the user the flexibility to operate the ad9762 in various configurations. possible output configurations include transformer coupled, resistor terminated, inverting/noninverting and differential amplifier outputs. the digital inputs are designed to be driven directly from various word generators, with the on-board option to add a resistor network for proper load termination. provisions are also made to operate the ad9762 with either the internal or external reference, or to exercise the pow er-down feature. refer to the application note an-420 ?sing the ad9760/ ad9762/ad9764-eb evaluation board?for a thorough description and operating instructions for the ad9762 evalua tion board.
ad9762 19 rev. b 1098765432 1 r4 10 9 8 7 6 5 4 3 2 1 r7 dvdd 10 9 8 7 6 5 4 3 2 1 r3 1098765432 1 dvdd r6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 p1 10 9 8 7 6 5 4 3 2 1 r5 dvdd 10 9 8 7 6 5 4 3 2 1 r1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c19 c1 c2 c25 c26 c27 c28 c29 16 pindip res pk 16 15 14 13 12 11 10 1 2 3 4 5 6 7 c30 c31 c32 c33 c34 c35 c36 16 pindip res pk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 clock dvdd dcom nc avdd comp2 iouta ioutb acom comp1 fs adj refio reflo sleep u1 ad976x avdd ct1 a 1 a r15 49.9 clk jp1 ab 3 2 1 j1 tp1 extclk c7 1 f c8 0.1 f avdd a c9 0.1 f tp8 2 avdd tp11 c11 0.1 f tp10 tp9 r16 2k tp14 jp4 c10 0.1 f out 1 out 2 tp13 r17 49.9 pdin j2 a a a avdd 3 jp2 tp12 tp7 a c6 10 f avcc b6 tp6 a c5 10 f avee b5 tp19 a agnd b4 tp18 tp5 c4 10 f tp4 avdd b3 tp2 dgnd b2 c3 10 f tp3 dvdd b1 r20 49.9 j3 c12 22pf a a r14 0 a 4 5 6 1 3 t1 j7 r38 49.9 j4 a a jp6a jp6b a r13 open c13 22pf c20 0 r12 open a b a jp7b b a jp7a r10 1k b a jp8 r9 1k a b a r35 1k jp9 r18 1k a 3 7 6 2 4 ad8047 c21 0.1 f a c22 1 f r36 1k c23 0.1 f a c24 1 f avee avcc r37 49.9 j6 a 3 7 6 2 4 1 2 3 jp5 c15 0.1 f a avee r46 1k c17 0.1 f a 1 2 3 jp3 a b avcc a cw r43 5k r45 1k c14 1 f a r44 50 extrefin j5 a r42 1k c16 1 f a avcc c18 0.1 f u7 6 2 4 a vin vout gnd ref43 98765432 1 r2 10 a 1098765432 1 dvdd r8 u6 a ad8047 out2 out1 u4 figure 59. ad9762 evaluation board schematic
ad9762 20 rev. b figure 60. silkscreen layer top figure 61. component side pcb layout (layer 1)
ad9762 21 rev. b figure 62. ground plane pcb layout (layer 2) figure 63. power plane pcb layout (layer 3)
ad9762 22 rev. b figure 64. solder side pcb layout (layer 4) figure 65. silkscreen layer bottom
ad9762 23 rev. b outline dimensions dimensions shown in inches and (mm). 28-lead, 300 mil soic (r-28) 0.0125 (0.32) 0.0091 (0.23) 8 0 0.0291 (0.74) 0.0098 (0.25) 45 0.0500 (1.27) 0.0157 (0.40) 28 15 14 1 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 28-lead, tssop (ru-28) 28 15 14 1 0.386 (9.80) 0.378 (9.60) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 c2201b 1 3/00 (rev. b) printed in u.s.a.

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